/*******************************************************************************
 *                                    ZLG
 *                         ----------------------------
 *                         innovating embedded platform
 *
 * Copyright (c) 2001-present Guangzhou ZHIYUAN Electronics Co., Ltd.
 * All rights reserved.
 *
 * Contact information:
 * web site:    https://www.zlg.cn
 *******************************************************************************/
#ifndef __HPM6E00_REGS_ESC_H
#define __HPM6E00_REGS_ESC_H

#ifdef __cplusplus
extern "C" {
#endif  /* __cplusplus*/

#include "core/include/hpm6e00_regs_base.h"
#include <stdint.h>

#define ESC_GPR_CFG0_CLK100_EN_MASK       (0x1 << ESC_GPR_CFG0_CLK100_EN_POS)
#define ESC_GPR_CFG0_CLK100_EN_POS        (13U)

#define ESC_PHY_CFG1_REFCK_25M_OE_MASK    (0x1 << ESC_PHY_CFG1_REFCK_25M_OE_POS)
#define ESC_PHY_CFG1_REFCK_25M_OE_POS     (3U)

typedef struct {
    volatile const  uint8_t  TYPE;                        /* 0x0: Type of EtherCAT controller */
    volatile const  uint8_t  REVISION;                    /* 0x1: Revision of EtherCAT controller */
    volatile const  uint16_t BUILD;                       /* 0x2: Build of EtherCAT controller */
    volatile const  uint8_t  FMMU_NUM;                    /* 0x4: FMMU supported */
    volatile const  uint8_t  SYNCM_NUM;                   /* 0x5: SyncManagers supported */
    volatile const  uint8_t  RAM_SIZE;                    /* 0x6: RAM Size */
    volatile const  uint8_t  PORT_DESC;                   /* 0x7: Port Descriptor */
    volatile const  uint16_t FEATURE;                     /* 0x8: ESC Feature supported */
    volatile const  uint8_t  RESERVED0[6];                /* 0xA - 0xF: Reserved */
    volatile const  uint16_t STATION_ADDR;                /* 0x10: Configured Station Address */
    volatile uint16_t STATION_ALS;                 /* 0x12: Configured Station Alias */
    volatile const  uint8_t  RESERVED1[12];               /* 0x14 - 0x1F: Reserved */
    volatile const  uint8_t  REG_WEN;                     /* 0x20: Register Write Enable */
    volatile const  uint8_t  REG_WP;                      /* 0x21: Register Write Protection */
    volatile const  uint8_t  RESERVED2[14];               /* 0x22 - 0x2F: Reserved */
    volatile const  uint8_t  ESC_WEN;                     /* 0x30: ESC Write Enable */
    volatile const  uint8_t  ESC_WP;                      /* 0x31: ESC Write Protection */
    volatile const  uint8_t  RESERVED3[14];               /* 0x32 - 0x3F: Reserved */
    volatile const  uint8_t  ESC_RST_ECAT;                /* 0x40: ESC Reset ECAT */
    volatile uint8_t  ESC_RST_PDI;                 /* 0x41: ESC Reset PDI */
    volatile const  uint8_t  RESERVED4[190];              /* 0x42 - 0xFF: Reserved */
    volatile const  uint32_t ESC_DL_CTRL;                 /* 0x100: ESC DL Control */
    volatile const  uint8_t  RESERVED5[4];                /* 0x104 - 0x107: Reserved */
    volatile const  uint16_t PHYSICAL_RW_OFFSET;          /* 0x108: Physical Read/Write Offset */
    volatile const  uint8_t  RESERVED6[6];                /* 0x10A - 0x10F: Reserved */
    volatile const  uint16_t ESC_DL_STAT;                 /* 0x110: ESC DL Status */
    volatile const  uint8_t  RESERVED7[14];               /* 0x112 - 0x11F: Reserved */
    volatile uint16_t AL_CTRL;                     /* 0x120: AL Control */
    volatile const  uint8_t  RESERVED8[14];               /* 0x122 - 0x12F: Reserved */
    volatile uint16_t AL_STAT;                     /* 0x130: AL Status */
    volatile const  uint8_t  RESERVED9[2];                /* 0x132 - 0x133: Reserved */
    volatile uint16_t AL_STAT_CODE;                /* 0x134: AL Status Code */
    volatile const  uint8_t  RESERVED10[2];               /* 0x136 - 0x137: Reserved */
    volatile uint8_t  RUN_LED_OVRD;                /* 0x138: RUN LED Override */
    volatile uint8_t  ERR_LED_OVRD;                /* 0x139: ERR LED Override */
    volatile const  uint8_t  RESERVED11[6];               /* 0x13A - 0x13F: Reserved */
    volatile const  uint8_t  PDI_CTRL;                    /* 0x140: PDI Control */
    volatile const  uint8_t  ESC_CFG;                     /* 0x141: ESC Configuration */
    volatile const  uint8_t  RESERVED12[12];              /* 0x142 - 0x14D: Reserved */
    volatile const  uint16_t PDI_INFO;                    /* 0x14E: PDI Information */
    volatile const  uint8_t  PDI_CFG;                     /* 0x150: PDI Configuration */
    volatile const  uint8_t  PDI_SL_CFG;                  /* 0x151: PDI Sync/Latch[1:0] Configuration */
    volatile uint16_t PDI_EXT_CFG;                 /* 0x152: PDI Extended Configuration */
    volatile const  uint8_t  RESERVED13[172];             /* 0x154 - 0x1FF: Reserved */
    volatile const  uint16_t ECAT_EVT_MSK;                /* 0x200: ECAT Event Mask */
    volatile const  uint8_t  RESERVED14[2];               /* 0x202 - 0x203: Reserved */
    volatile uint32_t PDI_AL_EVT_MSK;              /* 0x204: PDI AL Event Mask */
    volatile const  uint8_t  RESERVED15[8];               /* 0x208 - 0x20F: Reserved */
    volatile const  uint16_t ECAT_EVT_REQ;                /* 0x210: ECAT Event Request */
    volatile const  uint8_t  RESERVED16[14];              /* 0x212 - 0x21F: Reserved */
    volatile const  uint32_t AL_EVT_REQ;                  /* 0x220: AL Event Request */
    volatile const  uint8_t  RESERVED17[220];             /* 0x224 - 0x2FF: Reserved */
    volatile const  uint16_t RX_ERR_CNT[4];               /* 0x300 - 0x306: RX Error Counter */
    volatile const  uint8_t  FWD_RX_ERR_CNT[4];           /* 0x308 - 0x30B: Forwarded RX Error Counter */
    volatile const  uint8_t  ECAT_PU_ERR_CNT;             /* 0x30C: ECAT Processing Unit Error Counter */
    volatile const  uint8_t  PDI_ERR_CNT;                 /* 0x30D: PDI Error Counter */
    volatile const  uint8_t  RESERVED18[2];               /* 0x30E - 0x30F: Reserved */
    volatile const  uint8_t  LOST_LINK_CNT[4];            /* 0x310 - 0x313: Lost Link Counter */
    volatile const  uint8_t  RESERVED19[236];             /* 0x314 - 0x3FF: Reserved */
    volatile const  uint16_t WDG_DIV;                     /* 0x400: Watchdog Divider */
    volatile const  uint8_t  RESERVED20[14];              /* 0x402 - 0x40F: Reserved */
    volatile const  uint16_t WDG_TIME_PDI;                /* 0x410: Watchdog Time PDI */
    volatile const  uint8_t  RESERVED21[14];              /* 0x412 - 0x41F: Reserved */
    volatile const  uint16_t WDG_TIME_PDAT;               /* 0x420: Watchdog Time Process Data */
    volatile const  uint8_t  RESERVED22[30];              /* 0x422 - 0x43F: Reserved */
    volatile uint16_t WDG_STAT_PDAT;               /* 0x440: Watchdog Status Process Data */
    volatile const  uint8_t  WDG_CNT_PDAT;                /* 0x442: Watchdog Counter Process Data */
    volatile const  uint8_t  WDG_CNT_PDI;                 /* 0x443: Watchdog Counter PDI */
    volatile const  uint8_t  RESERVED23[188];             /* 0x444 - 0x4FF: Reserved */
    volatile const  uint8_t  EEPROM_CFG;                  /* 0x500: EEPROM Configuration */
    volatile uint8_t  EEPROM_PDI_ACC_STAT;         /* 0x501: EEPROM PDI Access State */
    volatile uint16_t EEPROM_CTRL_STAT;            /* 0x502: EEPROM Control/Status */
    volatile uint32_t EEPROM_ADDR;                 /* 0x504: EEPROM Address */
    volatile uint64_t EEPROM_DATA;                 /* 0x508: EEPROM Data */
    volatile uint16_t MII_MNG_CS;                  /* 0x510: MII Management Control/Status */
    volatile uint8_t  PHY_ADDR;                    /* 0x512: PHY Address */
    volatile uint8_t  PHY_REG_ADDR;                /* 0x513: PHY Register Address */
    volatile uint16_t PHY_DATA;                    /* 0x514: PHY Data */
    volatile const  uint8_t  MIIM_ECAT_ACC_STAT;          /* 0x516: MII Management ECAT Access State */
    volatile uint8_t  MIIM_PDI_ACC_STAT;           /* 0x517: MII Management PDI Access State */
    volatile uint8_t  PHY_STAT[4];                 /* 0x518 - 0x51B: PHY Port */
    volatile const  uint8_t  RESERVED24[228];             /* 0x51C - 0x5FF: Reserved */
    struct {
        volatile const  uint32_t LOGIC_START_ADDR;        /* 0x600: Logical Start Address */
        volatile const  uint16_t LENGTH;                  /* 0x604: Length */
        volatile const  uint8_t  LOGIC_START_BIT;         /* 0x606: Logical Start Bit */
        volatile const  uint8_t  LOGIC_STOP_BIT;          /* 0x607: Logical Stop Bit */
        volatile const  uint16_t PHYSICAL_START_ADDR;     /* 0x608: Physical Start Address */
        volatile const  uint8_t  PHYSICAL_START_BIT;      /* 0x60A: Physical Start Bit */
        volatile const  uint8_t  TYPE;                    /* 0x60B: Type */
        volatile const  uint8_t  ACTIVATE;                /* 0x60C: Activate */
        volatile const  uint8_t  RESERVED0[3];            /* 0x60D - 0x60F: Reserved */
    } FMMU[8];
    volatile const  uint8_t  RESERVED25[384];             /* 0x680 - 0x7FF: Reserved */
    struct {
        volatile const  uint16_t PHYSICAL_START_ADDR;     /* 0x800: Physical Start Address */
        volatile const  uint16_t LENGTH;                  /* 0x802: Length */
        volatile const  uint8_t  CONTROL;                 /* 0x804: Control */
        volatile const  uint8_t  STATUS;                  /* 0x805: Status */
        volatile uint8_t  ACTIVATE;                /* 0x806: Activate */
        volatile uint8_t  PDI_CTRL;                /* 0x807: PDI Control */
    } SYNCM[8];
    volatile const  uint8_t  RESERVED26[192];             /* 0x840 - 0x8FF: Reserved */
    volatile const  uint32_t RCV_TIME[4];                 /* 0x900 - 0x90C: Receive Time */
    volatile uint64_t SYS_TIME;                    /* 0x910: System Time */
    volatile const  uint64_t RCVT_ECAT_PU;                /* 0x918: Receive Time ECAT Processing Unit */
    volatile uint64_t SYS_TIME_OFFSET;             /* 0x920: System Time Offset */
    volatile uint32_t SYS_TIME_DELAY;              /* 0x928: System Time Delay */
    volatile const  uint32_t SYS_TIME_DIFF;               /* 0x92C: System Time Difference */
    volatile uint16_t SPD_CNT_START;               /* 0x930: Speed Counter Start */
    volatile const  uint16_t SPD_CNT_DIFF;                /* 0x932: Speed Counter Diff */
    volatile uint8_t  SYS_TIME_DIFF_FD;            /* 0x934: System Time Difference Filter Depth */
    volatile uint8_t  SPD_CNT_FD;                  /* 0x935: Speed Counter Filter Depth */
    volatile const  uint8_t  RCV_TIME_LM;                 /* 0x936: Receive Time Latch Mode */
    volatile const  uint8_t  RESERVED27[73];              /* 0x937 - 0x97F: Reserved */
    volatile const  uint8_t  CYC_UNIT_CTRL;               /* 0x980: Cyclic Unit Control */
    volatile uint8_t  SYNCO_ACT;                   /* 0x981: SYNC Out Unit Activation */
    volatile const  uint16_t PULSE_LEN;                   /* 0x982: Pulse Length of SyncSignals */
    volatile const  uint8_t  ACT_STAT;                    /* 0x984: Activation Status */
    volatile const  uint8_t  RESERVED28[9];               /* 0x985 - 0x98D: Reserved */
    volatile uint8_t  SYNC0_STAT;                  /* 0x98E: SYNC0 Status */
    volatile uint8_t  SYNC1_STAT;                  /* 0x98F: SYNC1 Status */
    volatile uint64_t START_TIME_CO;               /* 0x990: Start Time Cyclic Operation */
    volatile const  uint64_t NXT_SYNC1_PULSE;             /* 0x998: Next SYNC1 Pulse */
    volatile uint32_t SYNC0_CYC_TIME;              /* 0x9A0: SYNC0 Cycle Time */
    volatile uint32_t SYNC1_CYC_TIME;              /* 0x9A4: SYNC1 Cycle Time */
    volatile uint8_t  LATCH0_CTRL;                 /* 0x9A8: Latch0 Control */
    volatile uint8_t  LATCH1_CTRL;                 /* 0x9A9: Latch1 Control */
    volatile const  uint8_t  RESERVED29[4];               /* 0x9AA - 0x9AD: Reserved */
    volatile const  uint8_t  LATCH0_STAT;                 /* 0x9AE: Latch0 Status */
    volatile const  uint8_t  LATCH1_STAT;                 /* 0x9AF: Latch1 Status */
    volatile uint64_t LATCH0_TIME_PE;              /* 0x9B0: Latch0 Time Positive Edge */
    volatile uint64_t LATCH0_TIME_NE;              /* 0x9B8: Latch0 Time Negative Edge */
    volatile uint64_t LATCH1_TIME_PE;              /* 0x9C0: Latch1 Time Positive Edge */
    volatile uint64_t LATCH1_TIME_NE;              /* 0x9C8: Latch1 Time Negative Edge */
    volatile const  uint8_t  RESERVED30[32];              /* 0x9D0 - 0x9EF: Reserved */
    volatile const  uint32_t ECAT_BUF_CET;                /* 0x9F0: EtherCAT Buffer Change Event Time */
    volatile const  uint8_t  RESERVED31[4];               /* 0x9F4 - 0x9F7: Reserved */
    volatile const  uint32_t PDI_BUF_SET;                 /* 0x9F8: PDI Buffer Start Event Time */
    volatile const  uint32_t PDI_BUF_CET;                 /* 0x9FC: PDI Buffer Change Event Time */
    volatile const  uint8_t  RESERVED32[1024];            /* 0xA00 - 0xDFF: Reserved */
    volatile const  uint64_t PID;                         /* 0xE00: Product ID */
    volatile const  uint64_t VID;                         /* 0xE08: Vendor ID */
    volatile const  uint8_t  RESERVED33[240];             /* 0xE10 - 0xEFF: Reserved */
    volatile const  uint32_t DIO_OUT_DATA;                /* 0xF00: Digital I/O Output Data */
    volatile const  uint8_t  RESERVED34[12];              /* 0xF04 - 0xF0F: Reserved */
    volatile uint64_t GPO;                         /* 0xF10: General Purpose Outputs */
    volatile const  uint64_t GPI;                         /* 0xF18: General Purpose Inputs */
    volatile const  uint8_t  RESERVED35[96];              /* 0xF20 - 0xF7F: Reserved */
    volatile uint8_t  USER_RAM_BYTE0;              /* 0xF80: User Ram Byte 0 */
    volatile uint8_t  USER_RAM_BYTE1;              /* 0xF81: User Ram Byte 1 */
    volatile uint8_t  USER_RAM_BYTE2;              /* 0xF82: User Ram Byte 2 */
    volatile uint8_t  USER_RAM_BYTE3;              /* 0xF83: User Ram Byte 3 */
    volatile uint8_t  USER_RAM_BYTE4;              /* 0xF84: User Ram Byte 4 */
    volatile uint8_t  USER_RAM_BYTE5;              /* 0xF85: User Ram Byte 5 */
    volatile uint8_t  USER_RAM_BYTE6;              /* 0xF86: User Ram Byte 6 */
    volatile uint8_t  USER_RAM_BYTE7;              /* 0xF87: User Ram Byte 7 */
    volatile uint8_t  USER_RAM_BYTE8;              /* 0xF88: User Ram Byte 8 */
    volatile uint8_t  USER_RAM_BYTE9;              /* 0xF89: User Ram Byte 9 */
    volatile uint8_t  USER_RAM_BYTE10;             /* 0xF8A: User Ram Byte 10 */
    volatile uint8_t  USER_RAM_BYTE11;             /* 0xF8B: User Ram Byte 11 */
    volatile const  uint8_t  RESERVED36[2];               /* 0xF8C - 0xF8D: Reserved */
    volatile uint8_t  USER_RAM_BYTE14;             /* 0xF8E: User Ram Byte 14 */
    volatile uint8_t  USER_RAM_BYTE15;             /* 0xF8F: User Ram Byte 15 */
    volatile const  uint8_t  RESERVED37[3];               /* 0xF90 - 0xF92: Reserved */
    volatile uint8_t  USER_RAM_BYTE19;             /* 0xF93: User Ram Byte 19 */
    volatile const  uint8_t  RESERVED38[108];             /* 0xF94 - 0xFFF: Reserved */
    volatile uint32_t PDRAM;                       /* 0x1000: Process Data Ram */
    volatile const  uint8_t  RESERVED39[61436];           /* 0x1004 - 0xFFFF: Reserved */
    volatile uint32_t PDRAM_ALS;                   /* 0x10000: Process Data Ram Alias */
    volatile const  uint8_t  RESERVED40[61436];           /* 0x10004 - 0x1EFFF: Reserved */
    volatile uint32_t GPR_CFG0;                    /* 0x1F000: General Purpose Configure 0 */
    volatile uint32_t GPR_CFG1;                    /* 0x1F004: General Purpose Configure 1 */
    volatile uint32_t GPR_CFG2;                    /* 0x1F008: General Purpose Configure 2 */
    volatile const  uint8_t  RESERVED41[4];               /* 0x1F00C - 0x1F00F: Reserved */
    volatile uint32_t PHY_CFG0;                    /* 0x1F010: PHY Configure 0 */
    volatile uint32_t PHY_CFG1;                    /* 0x1F014: PHY Configure 1 */
    volatile const  uint8_t  RESERVED42[8];               /* 0x1F018 - 0x1F01F: Reserved */
    volatile uint32_t GPIO_CTRL;                   /* 0x1F020: GPIO Output Enable */
    volatile const  uint8_t  RESERVED43[12];              /* 0x1F024 - 0x1F02F: Reserved */
    volatile uint32_t GPI_OVERRIDE0;               /* 0x1F030: GPI low word Override value */
    volatile uint32_t GPI_OVERRIDE1;               /* 0x1F034: GPI high word Override value */
    volatile const  uint32_t GPO_REG0;                    /* 0x1F038: GPO low word read value */
    volatile const  uint32_t GPO_REG1;                    /* 0x1F03C: GPO high word read value */
    volatile const  uint32_t GPI_REG0;                    /* 0x1F040: GPI low word read value */
    volatile const  uint32_t GPI_REG1;                    /* 0x1F044: GPI high word read value */
    volatile const  uint8_t  RESERVED44[24];              /* 0x1F048 - 0x1F05F: Reserved */
    volatile const  uint32_t GPR_STATUS;                  /* 0x1F060: global status register */
    volatile const  uint8_t  RESERVED45[28];              /* 0x1F064 - 0x1F07F: Reserved */
    volatile uint32_t IO_CFG[9];                   /* 0x1F080 - 0x1F0A0: CTR IO Configure */
} hpm_esc_reg_t;

#define HPM_ESC ((hpm_esc_reg_t *)HPM_ESC_BASE)

#ifdef __cplusplus
}
#endif  /* __cplusplus  */
#endif
